Interrupts & Exceptions
Relevant source files
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Interrupt services in the Zephyr RTOS provide a framework for compile-time registration of interrupt handlers, allowing the system to respond to asynchronous hardware events with minimal latency. The kernel is designed to handle both standard interrupts (IRQs) and complex CPU exceptions across various architectures, including ARM Cortex-M, x86, ARC, and RISC-V. These services are integrated into the Kernel Services to support multi-threading and real-time responsiveness.
Sources: doc/introduction/index.rst:76, doc/introduction/index.rst:19-30
Interrupt Architecture and Management
The Zephyr interrupt subsystem manages the lifecycle of an interrupt from hardware trigger to handler execution. The architecture supports nested interrupts on specific platforms like ARC (non-FIRQ) and provides mechanisms to prevent user-mode threads from unauthorized modifications of the IRQ locking status.
Hardware-Agnostic Interaction
While the underlying hardware varies, Zephyr provides standardized functions like irq_lock() and irq_unlock(). In User Mode, these functions can be invoked without triggering a CPU fault, but the system ensures that unprivileged threads cannot read or modify the actual IRQ locking state, maintaining kernel integrity.
Sources: tests/arch/arm/arm_interrupt/README.txt:20-23
Interrupt Flow and Execution Context
When an interrupt occurs, the CPU transitions from thread mode to handler mode. The following diagram illustrates the high-level flow of interrupt handling and fault detection.
The kernel distinguishes between valid interrupts and "Spurious Interrupts," which are handled by dedicated spurious interrupt or exception handlers.
Sources: tests/arch/arm/arm_interrupt/README.txt:10-15
Exception and Fault Handling
Exceptions are synchronous events generated by the CPU in response to error conditions or specific instructions. Zephyr categorizes these as Fatal Errors, which can lead to a Kernel Oops or Kernel Panic.
Common Exception Types
- CPU Exceptions: Generic hardware-detected errors.
- Kernel Oops: Software-initiated fatal error for non-recoverable internal states.
- Kernel Panic: Severe system-level failure requiring immediate halt.
- Stack Overflow: Detected via hardware mechanisms (MPU/MMU) or software sentinel values.
Sources: tests/arch/arm/arm_interrupt/README.txt:48-75, doc/releases/release-notes-1.9.rst:37-41
Fault Categories and Descriptions
The following table summarizes common faults encountered during interrupt or thread execution, particularly on ARM Cortex-M architectures.
| Fault Type | Description | Source Detection |
|---|---|---|
| Null Pointer | Attempting to dereference a NULL address in privileged code. | CPU Exception |
| Usage Fault | Execution of undefined instructions or invalid state transitions. | CPU Exception |
| Hard Fault | Escalation of a fault when the specific handler cannot be executed. | CPU Exception |
| Stacking Error | Fault during exception frame context stacking, often indicating overflow. | Cortex-M Mechanism |
| Stack Overflow | Breach of the lowest 4 bytes of the stack memory region. | Stack Sentinel |
Sources: tests/arch/arm/arm_interrupt/README.txt:1-18, doc/releases/release-notes-1.9.rst:37-41
Security and Protection Mechanisms
Interrupt handling is a critical component of Zephyr's security posture. The system implements "Execution Protection" to ensure that interrupt handling does not compromise memory isolation.
Protection Strategies
- Stack Protection: Stack guards and sentinel values detect overruns during interrupt servicing.
- Thread Separation: Memory protection constraints are enforced at the time of context switch, which is often triggered by an interrupt.
- Monolithic Integrity: Static linking removes the risk of malicious code being dynamically loaded via interrupt vectors.
Sources: doc/security/security-overview.rst:110-131, doc/releases/release-notes-1.9.rst:37-41
Interrupt Security Flow
This sequence diagram shows how the system handles a fault occurring within an ISR context while maintaining security boundaries.
Legacy vs. Unified Interrupt API
Significant changes were introduced in version 1.6.0 with the "Unified Kernel," which streamlined how interrupts are registered and managed.
- Removal of Task IRQs: Legacy microkernel-specific task IRQs were removed in favor of a unified model.
- Static Registration: The kernel shifted toward compile-time registration of interrupt handlers to optimize resource usage on constrained devices.
Sources: doc/releases/release-notes-1.6.rst:23-26, doc/releases/release-notes-1.6.rst:216-218
Interrupts and exceptions in Zephyr are fundamental to its real-time performance and security. By leveraging hardware-specific features like MPUs and stack sentinels, the kernel provides a robust environment for handling asynchronous events while protecting the system from common fault conditions and security threats.