Access Types: RC and WC

The regif tool automates the generation of Verilog register interfaces from an Excel template. It supports a variety of field access types which define the behavior of register bits. Among these are RC (Read Clear) and RWC (Read/Write Clear), which are specialized types for handling interactions between hardware events and software access. These types are crucial for implementing status registers, interrupt flags, and control fields that require specific clearing mechanisms.

While the readme.md file mentions RC and WC (Write Clear), the implementation in regif.py provides RC and RWC. The behavior of the implemented RC type corresponds to a "Write-to-Clear" mechanism, often abbreviated as WC or W1C. This document details the specific implementation and behavior of the RC and RWC access types as defined in the source code.

Sources: regif.py:10-12, regif.py:70, readme.md:46-47

RC (Read, Write-Clear)

The RC access type is designed for status bits that are set by a hardware event and must be cleared by a software write operation. This is a common pattern for interrupt status registers, where software must explicitly acknowledge the event by writing to the register to clear the flag. Although named "Read Clear", the implementation is a "Write Clear" mechanism.

Sources: regif.py:70, regif.py:121-129

Behavior and Implementation

An RC field is implemented as a flip-flop with the following behavior:

1. Reset: On system reset, the field is initialized to 1'b0.
2. Set by Hardware: An external hardware event signal ({name}_hw_set) sets the field to 1'b1.
3. Clear by Software: A bus write (bmi_wr) to the register, with the corresponding bit in bmi_wdata set, clears the field back to 1'b0.

This logic is generated from the RC_ALWYAS_L0 template in regif.py.

// From RC_ALWYAS_L0 template
`ctrl_always_ff_begin(bmi_clk, bmi_rstn)
        {if_name}{bitsel} <= 1'b0;
    end else if({name}{hw}{syncd}{bitsel}) begin 
        {if_name}{bitsel} <= 1'b1;//RC
    end else if(bmi_wr && (bmi_addr==`{reg_name}) && bmi_wdata{bmibitsel}) begin 
        {if_name}{bitsel} <= 1'b0;//RC
    end

Source: regif.py:121-129

The following diagram illustrates the state transitions of an RC bit.

Clock Domain Crossing (CDC)

The regif tool can optionally generate logic to handle Clock Domain Crossing for the hardware event signal. If CDC is enabled (SYNC is not "SYNC" in the Excel sheet), a 2-flop synchronizer is instantiated to safely transfer the hardware set signal ({name}_hw_set) into the bmi_clk domain. A pulse generator then creates a single-cycle pulse ({name}_hw_set_syncd) in the target clock domain.

The following diagram shows the CDC logic for an RC field's hardware set signal.

RWC (Read/Write, Hardware-Clear)

The RWC access type defines a register field that is generally readable and writable by software, but can also be cleared to its default reset value by an external hardware event. This is useful for control registers that need to be reset to a known state by a hardware trigger without a full system reset.

Sources: regif.py:70, regif.py:155-158, regif.py:488

Behavior and Implementation

An RWC field is part of the main register write logic but also has a special clear condition.

1. Reset: On system reset, the field is set to its defined reset value (rstval).
2. Software Write: The field can be written with a new value via a standard bus write (bmi_wr).
3. Hardware Clear: An external hardware signal ({name}_hw_clc) forces the field back to its reset value. This clear has priority over the software write if it occurs in the else branch of the main write condition.

The hardware clear logic is generated from the RWC_RST_L1 template, which is placed within an else block of the main register write always block.

// From W_ALWAYS_L3 and ELSE_PART_L2 templates
`ctrl_always_ff_begin(bmi_clk, bmi_rstn)
    // ... reset logic for all fields ...
end else if(bmi_wr && (bmi_addr==`{reg_name})) begin
    // ... normal software write logic for RWC field ...
end else begin
    // ... other conditions ...
    // HW clear to reset value operation
    if({name}{hw}{syncd}) begin
        {if_name:{fd_align}}  <= {rstval:6}  ;//RWC
    end 
    // ... other conditions ...
end 

Sources: regif.py:134-138, regif.py:155-158, regif.py:485-491

The following diagram illustrates the logic for updating an RWC field.

Clock Domain Crossing (CDC)

Similar to the RC type, RWC fields support CDC synchronization for the hardware clear signal ({name}_hw_clc) if enabled. The implementation uses a 2-flop synchronizer and a pulse generator to ensure the clear signal is safely applied in the bmi_clk domain.

Sources: regif.py:182-189, regif.py:539, regif.py:918-921

Summary of Access Types

Sources: regif.py:70, regif.py:121-129, regif.py:155-158

Conclusion

The RC and RWC access types in regif provide powerful and flexible mechanisms for creating register fields that interact with both software and hardware events. RC fields are ideal for status and interrupt management, following a "set-by-hardware, clear-by-software" paradigm. RWC fields offer standard software read/write capability with the added feature of a hardware-triggered clear to a default state. The built-in, optional CDC handling for the associated hardware signals further enhances the robustness of the generated register interface, making it suitable for complex multi-clock-domain designs.