Excel Template: Defining FIFO
Relevant source files
The following files were used as context for generating this wiki page:The regif tool provides a mechanism to automatically generate Verilog RTL code for register interfaces from an Excel spreadsheet. Among its features is the ability to define a register as a FIFO (First-In, First-Out) interface. This is not a full FIFO implementation, but rather a standardized way to generate a write-strobe signal for a register address, which can then be used to push data into an external FIFO module.
This functionality is enabled by a simple keyword, FIFO_IF, in the register's definition within the Excel template. The tool parses this keyword and generates specific Verilog code to create a "push" signal, simplifying the integration of FIFO control logic within the generated register map. The overall project is licensed under the GPLv3 license.
Sources: readme.md:46, regif.py:12, LICENSE
Enabling the FIFO Interface
To designate a register as a FIFO interface, the user must include the keyword FIFO_IF within the register's description column ("reg_des") in the Excel template.
When the regif script processes the Excel file, the Reg class constructor checks for the presence of this string in the register's description field. If found, it sets the fifo_if attribute for that register object to True.
Sources: regif.py:420-423
# regif.py:420-423
class Reg:
def __init__(self, reg, regifdict):
self.__dict__.update(regifdict)
# ...
self.fifo_if = True if "FIFO_IF" in reg[2] else False
This boolean flag dictates the kind of Verilog that will be generated for the register.
Generated Verilog Logic
Instead of generating standard read/write register logic, a register marked with FIFO_IF results in specialized Verilog code tailored for a write-push operation.
Write-Push Signal Generation
The primary output for a FIFO-defined register is a _push signal. The generator creates a wire for this signal and an assign statement that asserts it for one cycle when a write operation (bmi_wr) occurs at the register's specific address.
The logic is generated from the FIFO_PUSH_L4 template string within the script.
Sources: regif.py:120-124
// regif.py:120-124
FIFO_PUSH_L4 = \
'''//-------------------------------------------------------------------
//{addr} : {reg_name:{reg_align}} {if_Comment}
wire {reg_name}_push ;
assign {reg_name}_push = bmi_wr && (bmi_addr==`{reg_name});
{fifo_filed_assign}\n'''
The following diagram illustrates the logic for generating the push signal.
This diagram shows that the generated push signal is asserted only when a write occurs to the correct register address.
Sources: regif.py:122-123
I/O and Port Generation
The generated _push signal is declared as an output of the register interface module. For a register named MY_FIFO_REG, the tool will generate an output port named MY_FIFO_REG_push.
The declars method within the RegFields class handles the creation of this output port when the fifo_if flag is true for the parent register.
Sources: regif.py:794-800
| Signal Name | Direction | Width | Description |
|---|---|---|---|
{reg_name}_push | output | 1 | Asserted for one bmi_clk cycle when a write occurs to this register's address. |
Table showing the generated I/O for a FIFO interface register.
Field Mapping Guidance
While the tool generates the push signal, it does not generate read logic for a FIFO interface. Instead, for any fields defined under the FIFO_IF register in the Excel sheet, it generates commented-out assign statements. These serve as a template or a guide for the designer to connect an external FIFO's read data bus to the corresponding field signals.
This is controlled by the FIFOMAP template string.
Sources: regif.py:105, 707-711
// regif.py:105
FIFOMAP = "//assign {pn:20} = fifo_rdata{section:8} ;\n"
For a WO (Write-Only) field named FIFO_DATA at [7:0] under a FIFO register, the tool would generate:
//assign FIFO_DATA = fifo_rdata[7:0] ;
FIFO Generation Flow
The following diagram shows the end-to-end process, from parsing the Excel file to generating the final Verilog code for a FIFO interface. The process relies on the xlrd library to read the .xls file.
This sequence diagram outlines the steps from script execution to the generation of Verilog FIFO push logic.
Summary
The FIFO_IF feature in regif provides a simple and standardized method for creating a write-strobe signal associated with a specific register address. By adding a keyword to the Excel template, developers can quickly generate the necessary Verilog to interface with external FIFO modules, without writing the boilerplate logic manually. This accelerates the hardware design process by automating the creation of common control signals within a register-based system.
Sources: readme.md:31, 46