Special Access Types (CP, BP, RWT, RWP)

Relevant source files

The following files were used as context for generating this wiki page:

• regif.py
• readme.md
• setup.py
• .github/workflows/python-publish.yml
• regif/regif_template.xls

The regif tool supports several special access types for register fields, which allow for more complex and controlled write behaviors than standard RW (Read-Write) or WO (Write-Only) types. These special types, defined in the input Excel file, enable the automatic generation of Verilog for features like conditional writing, bitwise write protection, and state toggling. The supported special access types include CP, BP, RWT, and RWP.

These types are validated against a predefined list within the script to ensure only supported access types are used. This mechanism allows for robust and feature-rich register interface generation directly from a high-level specification.

Sources: regif.py:68-75, readme.md:46-54

Access Type Summary

The following table provides a high-level overview of the special access types discussed in this document.

Access Type	Name	Description
CP	Condition Protection	A write to a protected field is only performed if the CP field is written with a specific value in the same bus transaction.
BP	Bitwise Protection	A write to a protected field is performed on a bit-by-bit basis, where each bit is masked by the corresponding bit in the BP field.
RWT	Read-Write-Toggle	Writing a '1' to a bit in an RWT field causes that bit to toggle its value. Writing a '0' has no effect.
RWP	Read-Write-Protectable	A field that is writable via the bus. The generated logic suggests it may have specific behaviors when combined with other hardware signals outside of a direct bus write.

Sources: regif.py:68-75, regif.py:633-661

CP (Condition Protection)

A field with type CP acts as a gate for writing to other fields within the same register. The write operation to the protected fields only proceeds if the value written to the CP field matches a pre-defined condition value (specified in the reset column for the CP field). This is useful for preventing accidental writes to critical configuration fields.

The logic is implemented in the RegFields.protect_w_L1 method, which generates Verilog based on the W_PROTECTE_L2 template.

Sources: regif.py:648-661, regif.py:160-163

Write Logic Flow

The diagram below illustrates the logic for a write operation involving a CP field.

Implementation

The core of the CP logic is captured in the W_PROTECTE_L2 Verilog template:

//CP(condtion protection) write
if(bmi_wdata{p_section} == {w_valid_val}) begin {cprotects}
end

• {p_section} refers to the bit-slice of the CP field.
• {w_valid_val} is the condition value.
• {cprotects} contains the write assignments for the fields protected by this CP field.

Sources: regif.py:160-163

BP (Bitwise Protection)

The BP access type provides a bitmask for write operations to other fields. When a write occurs, only the bits in the protected field that correspond to a '1' being written to the BP field are updated. This allows for fine-grained, bit-level updates to a register field.

The _protect_check method validates that a BP field and the field it protects have matching bit widths to ensure a valid bit-by-bit protection scheme. The Verilog generation is handled by RegFields.protect_w_L1 using the BP_L0 template.

Sources: regif.py:537-553, regif.py:635-647

Write Logic Flow

This diagram shows the bitwise write logic for a BP-protected field.

Implementation

The BP logic is generated using the BP_L0 template for standard protected fields and BP_RWT_L0 for RWT fields.

// For standard fields
if(bmi_wdata{bmibitselp:4}) {if_name}{bitsel:4} <= bmi_wdata{bmibitsel:4};//{types}

// For RWT fields
if(bmi_wdata{bmibitselp:4}) {if_name}{bitsel:4} <= ~{if_name}{bitsel:4};//{types}

• {bmibitselp} is the bit in the BP field.
• {if_name} is the name of the protected field.

Sources: regif.py:141-144

RWT (Read-Write-Toggle)

An RWT field allows bits to be toggled by writing a '1' to them. Writing a '0' has no effect on the bit's current state. This is commonly used for clearing status flags or generating single-cycle trigger pulses where the hardware action is triggered by the state change.

The regif script identifies RWT fields and generates toggle logic using the RWT_L1 template. If the RWT field is protected by a BP field, the BP_RWT_L0 template is used instead.

Sources: regif.py:483, regif.py:148-149, regif.py:141-142

Write Logic Flow

The toggle logic for an RWT field is straightforward.

Implementation

The Verilog for the toggle behavior is generated from the RWT_L1 template:

{tab}{if_name:{fd_align}}  <= bmi_wdata{section}? ~{if_name}:{if_name};//{type}

This ternary expression concisely implements the toggle logic: if the incoming write data bit is 1, the register bit is assigned its inverse (~{if_name}); otherwise, it's assigned its current value, resulting in no change.

Sources: regif.py:148-149

RWP (Read-Write-Protectable)

The RWP access type defines a field that is writable from the bus. It is included in the list of standard writable types (w_type) and is handled by the normal write logic during a bus write cycle.

The generated Verilog indicates a special behavior for RWP fields outside of a bus write cycle. In the else branch of the main write always block (which executes on clock edges when bmi_wr is not asserted for the register's address), RWP fields are assigned their reset value. This suggests a "write-pulsed" behavior, where the field holds a written value only as long as write operations continue, and resets otherwise. This can be useful for trigger registers that should be cleared automatically after being written.

Sources: regif.py:484, regif.py:673-679, regif.py:137-138

State Flow Diagram

The diagram below shows the state transitions for a bit in an RWP field.

Implementation

The dual behavior of RWP is implemented across two parts of the generated always block.

1. Bus Write: The field is treated as a normal writable field.

   // From W_L1 template, part of 'normal_wr'
   {tab}{if_name:{fd_align}}  <= bmi_wdata{section:7};//{type}
   

2. No Bus Write: The field is reset to its default value.

   // From W_RST_L1 template, part of 'fieldrwp' in the 'else' block
   {if_name:{fd_align}}  <= {rstval:14}  ;
   

Sources: regif.py:146-147, regif.py:137-138, regif.py:674-675

Conclusion

The special access types CP, BP, RWT, and RWP significantly enhance the functionality of the regif tool. They provide powerful, high-level abstractions for implementing complex hardware control and status register behaviors. By defining these types in an Excel sheet, developers can automatically generate validated, human-readable Verilog for features like conditional configuration, bit-masked writes, and self-clearing triggers, reducing manual coding effort and minimizing errors.