Access Type: RO (Read Only)

Relevant source files

The following files were used as context for generating this wiki page:

• regif.py
• readme.md
• setup.py

The RO (Read Only) access type is a fundamental feature of the regif tool, used to define register fields that can be read by a bus interface but cannot be written to. These fields typically reflect the status of hardware signals, providing a mechanism for software to monitor the state of the system without being able to alter it. The regif script parses an Excel file, and when a field is marked as RO, it generates specific Verilog HDL to implement this read-only behavior.

The RO type is one of several access types supported by the generator, including RW, WO, and RC. Its primary purpose is to create a one-way data path from hardware logic to the reading software interface.

Sources: readme.md:41, regif.py:70

Field Definition

In the regif workflow, register fields are defined in an Excel spreadsheet. A field is designated as Read Only by placing the string "RO" in the "RW" column for that field's row. The script validates this access type against a predefined list of allowed values.

Sources: regif.py:1415-1417, setup.py:22-25

Validation

The script ensures that the access type is valid using a regular expression. The field_format list defines the validation rules for all field properties.

Property	Regex Pattern	Example
RW	`(RW	RC

This table shows the validation rule for the access type column.

Sources: regif.py:70

Verilog Generation Logic

When the regif script processes a field defined as RO, it generates specific Verilog code to implement the read-only functionality. This involves creating an input port for the hardware signal and connecting it to the read data bus logic.

I/O Declaration

An RO field results in the generation of an input port in the Verilog module. This port is intended to be connected to the hardware signal that provides the status to be read.

The diagram below illustrates the logic within the Field.declars method for an RO field.

The Field.declars method checks the field type. If it is RO, it calls self.inputs() and self.inport() to generate the necessary Verilog.

• self.inputs(): Creates the input port declaration.
• self.inport(): Creates the port connection for module instantiation.

Sources: regif.py:1078-1082

An example of the generated code for an RO field named hw_status would be:

// In module port list
input [width-1:0] hw_status;

// In module instantiation
.hw_status (hw_status), //i

Sources: regif.py:84, regif.py:86

Read Path Implementation

During a read operation (bmi_rd is high) that targets a register containing an RO field, the value of the corresponding input port is driven onto the bmi_rdata bus.

The RegFields.read_express method constructs the logic for the read data multiplexer. For an RO field, it directly uses the field's name (which is an input port) in the concatenation that forms the bmi_rdata value.

This logic is part of a large case statement within an always block that is sensitive to the bus clock and read signal.

The diagram below shows the data flow for a read operation on a register with an RO field.

The core of this implementation is in the R_L2 and R_ALWAYS templates.

# regif.py:202-203
R_L2 = \
    '''\n            `{reg_name:{reg_name_align}} : begin {bmi}_rdvld <=1'b1; {bmi}_rdata <=  {{{_read}}} ;end'''

The _read variable is constructed in read_express. For an RO field, the code adds the field name directly to the list of signals to be concatenated.

# regif.py:860-863
            elif (fd.type == "RO"):
                _read += fd.name + bitwrap + ","
            else:
                _read += fd.if_name + bitwrap + ","

Sources: regif.py:202-203, regif.py:858-864

Write Path Behavior

RO fields are explicitly excluded from all write logic. The bus interface cannot modify their value.

• The w_block method in the RegFields class, which generates the write logic, does not have any specific handling for RO fields.
• The internal lists of writable field types (e.g., w_type, cg_type) do not include RO.
• If a register contains only RO and/or RESERVED fields, a comment //Read Only is generated instead of a write block.

Sources: regif.py:440-441, regif.py:841-843

Summary of Characteristics

The table below summarizes the key characteristics of the RO access type.

Characteristic	Description
Bus Read	Yes. Returns the current value of the corresponding hardware input signal.
Bus Write	No. Writes to the register address have no effect on RO fields.
Verilog Port	input. An input port is created to receive the signal from the hardware.
Internal Storage	No. RO fields do not have corresponding reg or wire storage within the _regif module; they are pass-through inputs.
Reset Value	Not applicable. The field's value is determined by the external hardware signal.
Lock Signal	No. The unlocktype list includes RO, meaning lock_sig is ignored for RO fields.

Sources: regif.py:968-971, regif.py:1261

Conclusion

The RO access type provides a simple and secure method for exposing hardware status to a software-accessible bus interface. By generating an input port and connecting it only to the read data path, the regif tool ensures that these status fields are immutable from the perspective of the bus, correctly implementing the read-only design intent. This is crucial for system stability and preventing accidental modification of critical hardware state indicators.