Excel Template: Defining Memory (MEM)

Relevant source files

The following files were used as context for generating this wiki page:

• regif.py
• readme.md
• setup.py
• regif/regif_template.xls
• img/regif.png

The regif tool provides a mechanism to generate register interface logic for memory or FIFO-like structures. While the project documentation lists "mem" as a supported scenario, the implementation within the source code is handled via a special FIFO_IF keyword. This keyword, when placed in a register's description within the Excel template, alters the generated Verilog to provide a simple write-strobe interface, suitable for pushing data into an external memory or FIFO block.

This page details how to use the FIFO_IF keyword in the Excel template to create a memory-write interface and explains the architecture of the generated RTL.

Sources: readme.md:50, regif.py:12, regif.py:389

Defining a Memory/FIFO Interface

To define a register as a memory or FIFO write port, the string FIFO_IF must be included in the register's description column (reg_des) in the Excel input file. The regif parser detects this keyword and flags the register internally to generate specialized logic.

The Reg class constructor checks for the presence of "FIFO_IF" in the register's description to set the self.fifo_if boolean property.

Sources: regif.py:389

Excel Template Configuration

The following table illustrates how to configure a register as a FIFO/memory write interface in the regif_template.xls.

Column	Example Value	Description
offset	0x0100	The memory-mapped address for the write operation.
regname	MEM_WDATA	The name of the register.
reg_des	Write data to memory FIFO_IF	A description for the register. Must contain FIFO_IF.
width	32	The data width of the register.
section	[31:0]	The bit range for the data field.
fd_name	WDATA	The name of the data field.
RW	WO	The access type. For a write-only interface, this should be WO.
reset	0	The reset value for the field.

Sources: regif.py:72-79, regif.py:389, regif.py:1332-1338

Generated Architecture

When FIFO_IF is detected for a register, the regif tool generates a write-strobe mechanism instead of a standard readable/writable register. This is handled by the Reg.write property, which conditionally calls self.fields.fifo_push_declar() instead of the standard self.fields.w_block().

Sources: regif.py:397-399

The following diagram shows the logic flow within the regif.py script when parsing a register definition.

This diagram illustrates the conditional logic path based on the presence of the FIFO_IF keyword.
Sources: regif.py:389, regif.py:397-399

Key Generated Components

The generated logic consists of a single-cycle pulse signal and commented-out assignment suggestions for connecting to an external module.

1. Write-Strobe Signal (_push): A wire named {reg_name}_push is created. This signal is asserted for one clock cycle when a write operation (bmi_wr) occurs at the register's specific address (bmi_addr).
2. Field Mapping: For each WO field in the register, a commented-out assign statement is generated. This serves as a template for the user to connect the bmi_wdata bus bits to the inputs of an external memory or FIFO.

The core logic is generated from the FIFO_PUSH_L4 and FIFOMAP string templates.

# Source: regif.py:122-126
FIFO_PUSH_L4 = \
    '''//-------------------------------------------------------------------
//{addr} : {reg_name:{reg_align}} {if_Comment}
wire   {reg_name}_push ;
assign {reg_name}_push = bmi_wr && (bmi_addr==`{reg_name});
{fifo_filed_assign}\n'''

# Source: regif.py:108
FIFOMAP = "//assign  {pn:20} = fifo_rdata{section:8} ;\n"

The fifo_push_declar() method in the RegFields class uses FIFO_PUSH_L4 to construct the final Verilog block.

Sources: regif.py:122-126, regif.py:715-723, regif.py:1033-1035

Data Flow Sequence

The sequence diagram below shows the interaction during a bus write to a register configured with FIFO_IF.

This diagram illustrates that the regif module provides a _push signal, and the user is responsible for using this signal to capture bmi_wdata in their external memory or FIFO logic.

Sources: regif.py:124-125

Summary

The memory interface feature in regif, identified by the FIFO_IF keyword, provides a lightweight and standardized method for creating write-only ports for external memory or FIFO components. Instead of instantiating a full register, the tool generates a simple write-strobe (_push signal) that is asserted when the CPU or bus master writes to the specified address. This simplifies the integration of memory-like blocks by providing the necessary bus interface glue logic while leaving the memory implementation itself to the designer.

Sources: readme.md:50, regif.py:389