Access Types: W1S and W1C

Relevant source files

The following files were used as context for generating this wiki page. Note: Only 3 files were provided, which is fewer than the required 5. The analysis is based on the available files.

• regif.py
• readme.md
• setup.py

The regif project documentation lists W1S (Write-1-to-Set) and W1C (Write-1-to-Clear) as supported access types for register fields. However, an analysis of the core script regif.py reveals that these types are not currently implemented in the Verilog generation logic or the input validation rules. This page details the discrepancy and analyzes how these types could be supported based on existing patterns in the codebase.

The project version analyzed is 1.3.3.

Sources: readme.md:43-44, regif.py, setup.py:9

Documentation vs. Implementation

There is a notable difference between the features listed in the readme.md file and the features implemented in the regif.py script.

Sources: readme.md, regif.py

readme.md Specification

The project's readme.md file explicitly lists W1S and W1C under the "Accesstype" section, indicating they are intended to be supported features.

## Accesstype
...
**RWP**
**W1S**
**W1C**

Sources: readme.md:41-45

regif.py Validation Logic

The core script regif.py uses a regular expression to validate the access type specified for each register field in the input Excel file. The list of valid types does not include W1S or W1C. Any field defined with these types would fail the static validation check.

The validation is defined in the field_format global variable:

# regif.py:65
field_format = [
    # ...
    ("RW     ", r"(RW|RC|BP|CP|RO|WO|RWW|RWC|RWT|RWP)\Z", "RW,RC,BP,CP,RO,WO,RWW,RWC,RWT,RWP only"),
    # ...
]

The following table summarizes the support status of register access types.

Access Type	Supported in regif.py	Documented in readme.md
RW	✅	✅
RO	✅	✅
WO	✅	✅
RC	✅	✅
WC	❌	✅
RWC	✅	❌
RWT	✅	✅
RWW	✅	❌
RWP	✅	✅
CP	✅	✅
BP	✅	✅
W1S	❌	✅
W1C	❌	✅

Sources: regif.py:65-72, readme.md:32-45

Code Generation Analysis

Since W1S and W1C are not recognized by the validation logic, no specific Verilog code generation templates or logic exist for them within regif.py. However, by examining the implementation of similar access types like RWT (Read-Write-Toggle), we can infer a potential implementation pattern.

Sources: regif.py:150-151, regif.py:651-653

Comparison with RWT (Write-1-to-Toggle)

The RWT access type provides a "write-1-to-toggle" functionality. If a bit in the write data (bmi_wdata) is '1', the corresponding bit in the register is toggled. This is implemented using the RWT_L1 template.

# regif.py:150-151
RWT_L1 = \
    "\n        {tab}{if_name:{fd_align}}  <= bmi_wdata{section}? ~{if_name}:{if_name};//{type}"

This logic provides a clear precedent for handling write-1-to-X operations. The diagram below illustrates the logic for an RWT field during a register write operation.

Sources: regif.py:150-151

Potential Implementation Pattern for W1S/W1C

Following the pattern of RWT, W1S (Write-1-to-Set) and W1C (Write-1-to-Clear) could be implemented with similar conditional Verilog assignments.

• W1S (Write-1-to-Set): If the corresponding bmi_wdata bit is 1, set the register bit to 1. Otherwise, it remains unchanged.
• W1C (Write-1-to-Clear): If the corresponding bmi_wdata bit is 1, clear the register bit to 0. Otherwise, it remains unchanged.

The diagram below shows the hypothetical logic for these two access types.

Required Modifications for Support

To fully implement W1S and W1C support in the regif tool, the following modifications to regif.py would be necessary:

#	File	Required Modification	Description
1	regif.py	Update field_format variable	Add W1S and W1C to the access type validation regex to allow them in the input Excel file. `r"(RW
2	regif.py	Define new Verilog templates	Create new template strings, for example W1S_L1 and W1C_L1, to generate the Verilog assignment logic.
3	regif.py	Update w_always_L3 generation	Integrate the new templates into the w_always_L3 function (or a similar block) to include the generated Verilog in the output file for fields with these types.
4	regif.py	Update declars method in Field class	Ensure correct I/O ports and internal signals are declared for fields of type W1S and W1C. This would likely follow the pattern for RW or RWT.

Sources: regif.py:68, regif.py:651-653, regif.py:863-899

Conclusion

The W1S and W1C access types are documented in the regif project but are not yet implemented. The core script regif.py lacks the necessary validation and code generation logic to support them. However, the existing implementation for the RWT access type provides a clear and straightforward pattern that could be adapted to add W1S and W1C functionality in a future version. Adding support would require updates to the input validation rules and the introduction of new Verilog generation templates.

Sources: readme.md:43-44, regif.py:68, 150-151