Advanced Feature: Clock Gating

Relevant source files

The following files were used as context for generating this wiki page:

• regif.py
• readme.md
• setup.py
• regif/regif_template.xls
• regif/init.py

The regif tool provides an advanced feature to generate clock-gated logic for specific register types within the Verilog RTL output. This feature is designed to reduce dynamic power consumption by disabling the clock to registers when they are not being written to. The implementation is controlled by a simple setting in the input Excel configuration file and affects the structure of the generated always blocks for writable registers.

This feature was introduced in version 1.30 and applies to RW, RWT, and WO register field types. When enabled, the tool generates a separate always block sensitive to a dedicated gated write clock (bmi_clk_wr_cg) and modifies the main always block to exclude these register types. The user is responsible for instantiating the actual clock gating cell in their design.

Sources: regif.py:12, readme.md:46

Configuration

Clock gating is a global setting for the entire register interface module. It is enabled by a specific value in the input Excel spreadsheet.

Sources: regif.py:1111

Enabling the Feature

To enable clock gating, place the value "YES" in cell K4 of the Excel register definition file. Any other value will disable the feature.

Cell	Parameter	Description
K4	rw_cg	Enables (YES) or disables clock gating for supported register types.

Sources: regif.py:1111, regif/regif_template.xls

The following diagram illustrates the configuration flow.

This diagram shows how the value in cell K4 of the input Excel file determines whether clock gating logic is generated.
Sources: regif.py:1111

Architecture and Implementation

When clock gating is enabled, regif alters the generated Verilog code by adding a new input port, modifying the logic generation for certain register types, and using specific Verilog code templates.

Sources: regif.py:130-140, 241-243, 448-454, 631-639

Generated Ports and Signals

A dedicated input port for the gated clock is added to the regif module.

Port Name	Direction	Description
bmi_clk_wr_cg	input	The gated clock signal for write operations. This port is only generated when clock gating is enabled.

The tool expects the user to instantiate a clock gating cell externally and connect its output to this port.

// Please instance manually outside like: 
// gate_cell  u_RW_cg_cell(.CLK(bmi_clk), .TSE(test_mode), .E(bmi_wr), .ECK(bmi_clk_wr_cg));

Sources: regif.py:241-243

The following diagram shows the architectural relationship between the user's design, the generated wrapper, and the core register file module.

This diagram illustrates that the user must provide the clock gating cell (gate_cell), which generates the bmi_clk_wr_cg signal used by the regif module.
Sources: regif.py:241-243, 301, 327

Logic Generation

The core of the implementation lies in the RegFields class, which separates register field types into different processing groups based on whether clock gating (rw_cg) is enabled.

1. Register Type Sorting: The script identifies which register fields are eligible for clock gating.

   • cg_type: A tuple defining the types that support clock gating: ("RW", "WO", "RWT").
   • cg_rst_list: A list of fields of cg_type that have a reset value.
   • cg_list: A list of RW and WO fields that are not write-protected.

   Sources: regif.py:448, 453-454

2. Conditional always Block Generation: The w_block method in the RegFields class conditionally calls w_cg_always_L3() to generate a dedicated always block for the clock-gated registers.

   # regif.py:674-675
   def w_block(self):
       # ...
       rw_cg_always = self.w_cg_always_L3() if (self.rw_cg) else ""
       # ...
   

   Sources: regif.py:674-675

3. Gated always Block Template: The w_cg_always_L3 method uses the W_CG_ALWAYS_L3 Verilog template. This always block is sensitive to the bmi_clk_wr_cg signal, ensuring that the registers within it only update when a write occurs.

   // regif.py:134-138
   {always_ff_begin}{rw_rst}
   end else if(bmi_wr && (bmi_addr==`{reg_name})) begin{rw_wr}{rwt_wr}{protect_wr}
   end 
   

   Note: The {always_ff_begin} macro resolves to an always block sensitive to posedge bmi_clk_wr_cg if clock gating is active, although the template string itself is generic. The key is that the logic is separated into a block that can be driven by a gated clock. The script generates a separate always block for non-gated fields sensitive to the main bmi_clk.

   Sources: regif.py:134-138, 631-639

The following sequence diagram shows how the regif script processes the configuration to generate the final Verilog.

This diagram shows the internal flow, from reading the Excel file to invoking the correct methods (w_cg_always_L3) to generate clock-gated logic.
Sources: regif.py:1111, 1144, 674-675, 631

Supported Register Types

Clock gating is only applied to a specific subset of register field access types.

Access Type	Clock Gating Support	Description
RW	Yes	Read/Write fields are placed in the gated always block.
WO	Yes	Write-Only fields are placed in the gated always block.
RWT	Yes	Read/Write-Toggle fields are placed in the gated always block.
RWC, RWP, RWW	No	These types are handled in a separate, non-gated always block.
RO, RC	No	These types are either read-only or have separate clear logic not tied to bmi_wr.

Sources: regif.py:448, 451-452

Summary

The clock gating feature in regif is a powerful tool for optimizing power in the generated hardware. By setting a single cell in the input Excel file, developers can instruct the tool to partition the register write logic. Writable fields of type RW, WO, and RWT are moved into a dedicated always block intended to be driven by a gated clock, bmi_clk_wr_cg. This isolates the switching activity to only when write operations are active, reducing overall dynamic power consumption. The responsibility for instantiating the physical clock gating cell lies with the user, providing design flexibility while automating the RTL modification process.

Sources: regif.py, readme.md, setup.py